Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines
نویسندگان
چکیده
منابع مشابه
Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines
Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computationintensive applications. With steady advances in silicon technology, as predicted by Moore’s Law, FieldProgrammable Gate Array (FPGA) technologies have enabled the implementation...
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HERA (HEterogeneous Reconfigurable Architecture) is an FPGA-based mixed-mode reconfigurable computing system that we have designed and implemented for the simultaneous execution of a variety of parallel processing modes. These modes are SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, MultipleData) and M-SIMD (Multiple-SIMD). Each processing element (PE) is centered on a si...
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In this paper we consider a direct method to solve a sparse unsymmetric system of linear equations Ax = b, which is the Gaussian elimination. This elimination consists in explicitly factoring the matrix A into the product of L and U , where L is a unit lower triangular matrix, and U is an upper triangular matrix, followed by solving LUx = b one factor at a time. One of the main characteristics ...
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Several message passing-based parallel solvers have been developed for general (nonsymmetric) sparse LU factorization with partial pivoting. Existing solvers were mostly deployed and evaluated on parallel computing platforms with high message passing performance (e.g., 1–10 μs in message latency and 100–1000 Mbytes/sec in message throughput) while little attention has been paid on slower platfo...
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ژورنال
عنوان ژورنال: Concurrency and Computation: Practice and Experience
سال: 2004
ISSN: 1532-0626,1532-0634
DOI: 10.1002/cpe.748